HD6417751 Datasheet, PDF (462/1105 Pages) Renesas Technology Corp – SuperH RISC engine

13.3.7 PCMCIA Interface
In the SH7751 Series, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external
memory space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in
JEIDA specification version 4.2 (PCMCIA2.1).
Figure 13.44 shows an example of PCMCIA card connection to the SH7751 Series. To enable
active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being
supplied), a 3-state buffer must be connected between the SH7751 Series bus interface and the
PCMCIA cards.
As operation in big endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard, this
LSI supports only little-endian mode setting and the little-endian mode PCMCIA interface.
When the MMU is on, PCMCIA interface can be set in MMU page units, and there is a choice of
8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory,
8-bit I/O space, 16-bit I/O space, or dynamic bus sizing. See section 3, Memory Management Unit
(MMU), for details of the setting method. When the MMU is off, the setting of bits SA2 to SA0 of
PTEA is always used for access.
SA2
SA1
SA0
Description
0
0
0
Reserved (Setting prohibited)
1
Dynamic I/O bus sizing
1
0
8-bit I/O space
1
16-bit I/O space
1
0
0
8-bit common memory
1
16-bit common memory
1
0
8-bit attribute memory
1
16-bit attribute memory
When the MMU is on, wait cycles in a bus access can be set in MMU page units. See section 3,
Memory Management Unit (MMU), for details of the setting method. When the MMU is off,
access is always performed according to the setting of the TC bit in PTEA. When TC is cleared to
0, bits A5W2–A5W0 in wait control register 2 (WCR2) and bits A5PCW1–A5PCW0, A5TED2–
A5TED0, and A5TEH2–A5TEH0 in the PCMCIA control register (PCR) are selected. When TC
is set to 1, bits A6W2–A6W0 in WCR2 and bits A6PCW1–A6PCW0, A6TED2–A6TED0, and
A6TEH2–A6TEH0 in PCR are selected.
Access to a PCMCIA interface area by the DMAC is always performed using the DMAC’s
CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values.
AnPCW1–AnPCW0 specify the number of wait states to be inserted in a low-speed bus cycle; a
value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for
Rev. 3.0, 04/02, page 422 of 1064