HD6417751 Datasheet, PDF (879/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.17 PCI Control Register (PCICR)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
— TRDSGL BYTESWAP
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R/W
R/W
PP Bus-R/W: R
R
R
R
R
R
R/W
R/W
Bit: 7
6
PCIPUP BMABT
Initial value: 0
0
PCI-R/W: R
R
PP Bus-R/W: R/W
R/W
5
MD10
0/1*
R
R
4
MD9
0/1*
R
R
3
SERR
0
R
R/W
2
INTA
0
R
R/W
1
0
RSTCTL CFINIT
0
0
R
R
R/W
R/W
Note: * The value of the external pin is sampled in a power-on reset by means of the #$% pin.
The PCI control register (PCICR) is a 32-bit register that monitors the status of the mode pin at
initialization and controls the basic operation of the PCIC. Bits 5 (MD10) and 4 (MD9) are read-
only bits from the PP bus. Other bits are read/write bits. Bits 9 (TRDSGL) and 8 (BYTESWAP)
are read/write bits from the PCI bus. Other bits are read-only.
In PCIC host operation, a software reset can be applied to the PCI bus by means of bit 1
(RSTCTL) of PCICR. When a software reset is executed, the 3&,567 pin is asserted and the
internal state of the PCIC is initialized.
The PCICR register is initialized at a power-on reset to H'000000*0 (bits 7 and 6 are initialized to
B'00, and bits 5 and 4 sample the value of mode pins 9 and 10). At a software reset, bit 1
(RSTCTL) is not initialized. All other bits are initialized in the same way as at a software reset.
Rev. 3.0, 04/02, page 839 of 1064