HD6417751 Datasheet, PDF (1057/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 23.29 Peripheral Module Signal Timing (2)
HD6417751VF133
*2
Module Item
Symbol Min Max
TMU,
Timer clock pulse t_TCLKWH 4
—
RTC
width (high)
Timer clock pulse t_TCLKWL
4
—
width (low)
Timer clock rise t_TCLKr
—
0.8
time
Timer clock fall
t_TCLKf
—
0.8
time
Oscillation
settling time
t_ROSC
—
3
SCI
Input clock cycle t_Scyc
4
—
(asynchronous)
Input clock cycle t_Scyc
6
—
(synchronous)
Input clock pulse t_SCKW
width
0.4 0.6
Input clock rise
t_SCKr
time
—
0.8
Input clock fall
t_SCKf
time
—
0.8
Transfer data
t_TXD
—
30
delay time
Receive data
t_RXS
setup time
(synchronous)
0.8 —
Receive data
t_RXH
hold time
(synchronous)
0.8 —
I/O
ports
Output data
delay time
t_PORTD
—
8
Input data setup
time
t_PORTS
3.5 —
Input data hold
time
t_PORTH
1.5 —
HD6417751BP167
HD6417751BP167I
HD6417751F167
HD6417751F167I
*3
Min
Max
Unit
4
—
Pcyc*¹
4
—
Pcyc*¹
—
0.8
Pcyc*¹
—
0.8
Pcyc*¹
—
3
s
4
—
Pcyc*¹
6
—
Pcyc*¹
0.4
0.6
—
0.8
—
0.8
t_Scyc
Pcyc*¹
Pcyc*¹
—
30
ns
0.8
—
Pcyc*¹
0.8
—
Pcyc*¹
—
8
ns
3.5
—
ns
1.5
—
ns
Figure Notes
23.59
23.59
23.59
23.59
23.60
23.61
23.61
23.61
23.61
23.61
23.62
23.62
23.62
23.63
23.63
23.63
Rev. 3.0, 04/02, page 1017 of 1064