HD6417751 Datasheet, PDF (790/1105 Pages) Renesas Technology Corp – SuperH RISC engine

19.5 Interrupt Response Time
The time from generation of an interrupt request* until interrupt exception handling is performed
and fetching of the first instruction of the exception handler is started (the interrupt response time)
is shown in table 19.8.
Note: * Including the case where the mask bit (IMASK) in SR is changed, and a new interrupt is
generated.
Table 19.8 Interrupt Response Time
Number of States
Item
NMI
RL
Peripheral
Modules
Notes
Time for priority decision and 1Icyc + 4Bcyc 1Icyc + 7Bcyc 1Icyc + 2Bcyc
SR mask bit comparison*
Wait time until end of
sequence being executed by
CPU
S – 1 (≥ 0) ×
Icyc
S – 1 (≥ 0) ×
Icyc
S – 1 (≥ 0) ×
Icyc
Time from interrupt exception
handling (save of SR and PC)
until fetch of first instruction of
exception handler is started
4 × Icyc
4 × Icyc
4 × Icyc
Response
time
Total
5Icyc + 4Bcyc 5Icyc + 7Bcyc 5Icyc + 2Bcyc
+ (S – 1)Icyc + (S – 1)Icyc + (S – 1)Icyc
Minimum
case
13Icyc
19Icyc
9Icyc
When Icyc:
Bcyc = 2:1
Maximum
case
36 + S Icyc
60 + S Icyc
20 + S Icyc
When Icyc:
Bcyc = 8:1
Icyc: One cycle of internal clock supplied to CPU, etc.
Bcyc: One CKIO cycle
S: Latency of instruction
Note: * In the SH7751, this includes the case where the mask bit (IMASK) in SR is changed and a
new interrupt is generated.
Rev. 3.0, 04/02, page 750 of 1064