HD6417751 Datasheet, PDF (130/1105 Pages) Renesas Technology Corp – SuperH RISC engine

• EMODE: Cache-double-mode bit
Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in
the SH7751. The EMODE bit cannot be modified while the cache is in use.
0: SH7751-compatible-mode^*1 (Initial value)
1: Cache-double-mode
Note: *1 Address allocation in OC index mode and RAM mode is not compatible with that in
RAM mode.
• IIX: IC index enable bit
0: Effective address bits [12:5] used for IC entry selection
1: Effective address bits [25] and [11:5] used for IC entry selection
• ICI: IC invalidation bit
When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns
0 when read.
• ICE: IC enable bit
Indicates whether or not the IC is to be used. When address translation is performed, the IC
cannot be used unless the C bit in the page management information is also 1.
0: IC not used
1: IC used
• OIX: OC index enable bit^*2
0: Effective address bits [13:5] used for OC entry selection
1: Effective address bits [25] and [12:5] used for OC entry selection
Note: *2 In the SH7751R, clear the OIX bit to 0 when the ORA bit is 1.
• ORA: OC RAM enable bit^*3
When the OC is enabled (OCE = 1), the ORA bit specifies whether the 8 kbytes from entry
128 to entry 255 and from entry 384 to entry 511 of the OC are to be used as RAM. When the
OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.
0: 16 kbytes used as cache
1: 8 kbytes used as cache, and 8 kbytes as RAM
Note: *3 In the SH7751R, clear the ORA bit to 0 when the OIX bit is 1.
• OCI: OC invalidation bit
When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always
returns 0 when read.
Rev. 3.0, 04/02, page 90 of 1064