HD6417751 Datasheet, PDF (502/1105 Pages) Renesas Technology Corp – SuperH RISC engine

If the SH7751 Series is specified as the master in a power-on reset, it will not accept bus requests
from the slave until the %5(4 enable bit (BCR1.BREQEN) is set to 1.
To ensure that the slave processor does not access memory requiring initialization before use, such
as DRAM and synchronous DRAM, until initialization is completed, write 1 to the %5(4 enable
bit after initialization ends.
Before setting self-refresh mode in standby mode, etc., write 0 to the %5(4 enable bit to
invalidate the %5(4 signal from the slave. Write 1 to the %5(4 enable bit only after the master
has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode.
13.3.15 Notes on Usage
Refresh: Auto refresh operations stop when a transition is made to standby mode or deep-sleep
mode. If the memory system requires refresh operations, set the memory in the self-refresh state
prior to making the transition to standby mode or deep-sleep mode.
Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master
mode does not release bus privileges. In systems performing bus arbitration, make the transition to
standby mode or deep-sleep mode only after setting the bus privilege release enable bit
(BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit
remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or
deep-sleep mode.
Simultaneous Use of Refresh and Bus Arbitration: With the SH7751, when performing bus
arbitration using the external device and %5(4 signal, the following two failures may occur.
• When a %5(4 signal is input from the external device while using DMA transfer or target
transfer by the PCIC, and DRAM/synchronous DRAM is set to CAS-before-RAS refresh and
auto-refresh in master mode (MD7 = 1), bus arbitration may not be performed correctly and
this LSI may hang up.
• When a %5(4 signal is input from the external device while DRAM/synchronous DRAM is
set to CAS-before-RAS refresh and auto-refresh in master mode (MD7 = 1), assertion of the
%$&. signal (low-level) in response to the %5(4 signal may be for only one cycle at CKIO.
Both above phenomena can be avoided by not using the %5(4 signal. If the %5(4 signal is to be
used, disable refresh operations during normal operation. If refresh operations are required, carry
them out at one time with the BREQEN bit in BCR1 cleared to 0.
Rev. 3.0, 04/02, page 462 of 1064