HD6417751 Datasheet, PDF (520/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in
DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
the transfer enabled state is not entered even if the DE bit is set to 1.
Bit 1: TE
0
Description
Number of transfers specified in DMATCR not completed
[Clearing conditions]
• When 0 is written to TE after reading TE = 1
• In a power-on or manual reset, and in standby mode
(Initial value)
1
Number of transfers specified in DMATCR completed
Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel.
Bit 0: DE
0
1
Description
Operation of corresponding channel is disabled
Operation of corresponding channel is enabled
(Initial value)
When auto-request is specified (with RS3–RS0), transfer is begun when this bit is set to 1. In the
case of an external request or on-chip peripheral module request, transfer is begun when a transfer
request is issued after this bit is set to 1. Transfer can be suspended midway by clearing this bit to
0.
Even if the DE bit has been set, transfer is not enabled when TE is 1, when DME in DMAOR is 0,
or when the NMIF or AE bit in DMAOR is 1.
Rev. 3.0, 04/02, page 480 of 1064