HD6417751 Datasheet, PDF (77/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0–
XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0–
FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1).
FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating-
point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–
XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix
XMTRX.
Register values after a reset are shown in table 2.1.
Table 2.1 Initial Register Values
Type
Registers
Initial Value*
General registers
R0_BANK0–R7_BANK0,
R0_BANK1–R7_BANK1,
R8–R15
Undefined
Control registers SR
MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,
I3–I0 = 1111 (H'F), reserved bits = 0, others
undefined
GBR, SSR, SPC, SGR,
DBR
Undefined
VBR
H'00000000
System registers MACH, MACL, PR, FPUL Undefined
PC
H'A0000000
FPSCR
H'00040001
Floating-point
registers
FR0–FR15, XF0–XF15 Undefined
Note: * Initialized by a power-on reset and manual reset.
The register configuration in each processor mode is shown in figure 2.2.
Switching between user mode and privileged mode is controlled by the processor mode bit (MD)
in the status register.
Rev. 3.0, 04/02, page 37 of 1064