HD6417751 Datasheet, PDF (673/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Section 16 Serial Communication Interface with FIFO
(SCIF)
16.1 Overview
The SH7751 Series is equipped with a single-channel serial communication interface with built-in
FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform
asynchronous serial communication.
Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast,
efficient, and continuous communication.
16.1.1 Features
SCIF features are listed below.
• Asynchronous serial communication
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be carried
out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
There is a choice of 8 serial data transfer formats.
 Data length: 7 or 8 bits
 Stop bit length: 1 or 2 bits
 Parity: Even/odd/none
 Receive error detection: Parity, framing, and overrun errors
 Break detection: If the receive data following that in which a framing error occurred is also
at the space “0” level, and there is a frame error, a break is detected. When a framing error
occurs, a break can also be detected by reading the RxD2 pin level directly from the serial
port register (SCSPTR2).
• Full-duplex communication capability
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK2 pin
Rev. 3.0, 04/02, page 633 of 1064