HD6417751 Datasheet, PDF (958/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Target configuration read transfer data alignment (configuration register
Configuration register
31
0
B3 B2 B1 B0
PCI bus
31
0
B3 B2 B1 B0
PCI bus)
BE
H’0 to H’F
SH7751 target configuration write transfer data alignment (PCI bus
Configuration register
31
0
B3 B2 B1 B0
PCI bus
31
0
B3 B2 B1 B0
configuration register)
BE
H’0 to H’F
SH7751R target configuration transfer data alignment (PCI bus configuration register)
Configuration register
31
0
B3 B2 B1 B0
PCI bus
31
0
B3 B2 B1 B0
BE
0000
31
0
B3 B2 B1
31
0
B3 B2 B1
0001
31
0
B3 B2 B0
31
0
B3 B2 B0
0010
31
0
B3 B2
31
0
B3 B2
0011
31
0
B3 B1 B0
31
0
B3 B1 B0
0100
31
0
B3 B1 B0
31
0
B3 B1 B0
0100
31
0
B3 B1
31
0
B3 B1
0101
31
0
B3
B0
31
0
B3
B0
0110
31
0
B3
31
0
B3
0111
31
0
B2 B1 B0
31
0
B2 B1 B0
1000
31
0
B2 B1
31
0
B2 B1
1001
31
0
B2 B0
31
0
B2 B0
1010
31
0
B2
31
0
B2
1011
31
0
B1 B0
31
0
B1 B0
1100
31
0
B1
31
0
B1
1101
31
0
B0
31
0
B0
1110
31
0
31
0
1111
Figure 22.23 Data Alignment at Target Configuration Transfer
(Both Big Endian and Little Endian)
Rev. 3.0, 04/02, page 918 of 1064