HD6417751 Datasheet, PDF (265/1105 Pages) Renesas Technology Corp – SuperH RISC engine

9.4.2 Exit from Deep Sleep Mode
As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip
peripheral module) or a reset.
9.5 Pin Sleep Mode
9.5.1 Transition to Pin Sleep Mode
Changing the 6/((3 pin to the low level causes the SH7751 Series to make a transition to sleep
mode.
To ensure that memory is correctly refreshed, use this function when the DSLP bit of STBCR2 is
set to 0.
9.5.2 Exit from Pin Sleep Mode
Setting the 6/((3 pin level high causes the SH7751 Series to return to the normal state. The pin
sleep mode is also canceled when the conditions specified in section 9.3.2, “Exit From Sleep
Mode” are satisfied.
In a power-on reset, the 6/((3 pin should be fixed high.
9.6 Standby Mode
9.6.1 Transition to Standby Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches
from the program execution state to standby mode. In standby mode, the on-chip peripheral
modules halt as well as the CPU. Clock output from the CKIO pin is also stopped.
The CPU and cache register contents are retained. Some on-chip peripheral module registers are
initialized. The state of the peripheral module registers in standby mode is shown in table 9.4.
Rev. 3.0, 04/02, page 225 of 1064