HD6417751 Datasheet, PDF (385/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS down mode is used, set BE to 1.
Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both
designated as synchronous DRAM interface.
Bit 31: RASD
Description
0
Normal mode
(Initial value)
1
RAS down mode
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is
used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface.
Bit 30: MRSET
0
1
Description
All-bank precharge
Mode register setting
(Initial value)
Bits 26 to 24, 22, and 18—Reserved: These bits should only be written with 0.
Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0)
(Synchronous DRAM: auto- and self-refresh both enabled, DRAM: auto- and self-refresh both
enabled)
Bit 29: TRC2
0
1
Bit 28: TRC1
0
1
0
1
Bit 27: TRC0
0
1
0
1
0
1
0
1
RAS Precharge Time
Immediately after Refresh
0
(Initial value)
3
6
9
12
15
18
21
Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set.
Bit 23: TCAS
0
1
CAS Negation Period
1
2
(Initial value)
Rev. 3.0, 04/02, page 345 of 1064