HD6417751 Datasheet, PDF (858/1105 Pages) Renesas Technology Corp – SuperH RISC engine

specifications. Bits 31 to 8 (class code) set the device functions. The chip logic version can be
read from bits 7 to 0 (revision ID).
Bits 31 to 8 can be written to from the PP bus. Bits 7 to 0 are fixed in hardware.
The PCICONF2 register class codes are not initialized at a reset. They must be initialized while
CFINIT (bit 0) of the PCI control registers (PCICR) is cleared.
Bits 31 to 24—Base Class Code (CLASS23 to 16): These bits indicate the base class code. For
details of setting values, refer to table 22.5.
Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)
CLASS23 to 16
Base Class
H'00
H'01
H'02
H'03
H'04
H'05
H'06
H'07
H'08
H'09
H'0A
H'0B
H'0C
H'0D to H'FE
H'FF
Meaning
Device designed prior to class code being defined
High-capacity storage controller
Network controller
Display controller
Multimedia device
Memory controller
Bridge device
Simple communication device
Basic peripheral device
Input device
Docking station
Processor
Serial bus controller
Reserved
Device not categorized in defined class
Bits 23 to 16—Sub Class Codes (CLASS15 to 8): For details, please see Appendix D, Pin
Functions of the PCI Local Bus Specifications, Revision 2.1.
Bits 15 to 8—Register Level Programming Interface (CLASS7 to 0): For details, please see
Appendix D, Pin Functions of the PCI Local Bus Specifications, Revision 2.1.
Bits 7 to 0—Revision ID (REVID7 to 0): Shows the PCIC revision. The initial value differs
according to the logic version of the chip.
Rev. 3.0, 04/02, page 818 of 1064