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| HD6417751 Datasheet, PDF (1011/1105 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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CKIO
A25âA0
RD/
D31âD0
(read)
D31âD0
(write)
TS1
T1
T2
TH1
tAD
tCSD
tRWD
tRSD
tRSD
tAD
tCSD
tRWD
tRSD
tWED1
tWDD
tRDS
tRDH
tWEDF tWEDF
tWDD
tWDD
tBSD
tBSD
DACKn
(SA: IO â memory)
tDACD
DACKn
(SA: IO â memory)
tDACD
tDACDF
DACKn
(DA)
tDACD
tDACD
tDACDF
tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time
Insertion, AnS = 1, AnH = 1)
Rev. 3.0, 04/02, page 971 of 1064
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