HD6417751 Datasheet, PDF (416/1105 Pages) Renesas Technology Corp – SuperH RISC engine

When software wait insertion is specified by WCR2, the external wait input 5'< signal is also
sampled. 5'< signal sampling is shown in figure 13.11. A single-cycle wait is specified as a
software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore,
the 5'< signal has no effect if asserted in the T1 cycle or the first Tw cycle. The 5'< signal is
sampled on the rising edge of the clock.
CKIO
A25–A0
T1
Tw
Twe
T2
RD/
(read)
D31–D0
(read)
(write)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by 5'< Signal)
Rev. 3.0, 04/02, page 376 of 1064