HD6417751 Datasheet, PDF (452/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
TRr1 TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc
RD/
D63–D0
CKE
Figure 13.36 Synchronous DRAM Auto-Refresh Timing
• Self-Refreshing
Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses
are generated within the synchronous DRAM. Self-refreshing is activated by setting both the
RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal
is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh
mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared,
command issuance is disabled for the number of cycles specified by bits TRC2–TRC0 in
MCR. Self-refresh timing is shown in figure 13.37. Settings must be made so that self-refresh
clearing and data retention are performed correctly, and auto-refreshing is performed at the
correct intervals. When self-refreshing is activated from the state in which auto-refreshing is
set, or when exiting standby mode other than through a power-on reset, auto-refreshing is
restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If
the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this
time should be taken into consideration when setting the initial value of RTCNT. Making the
RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state
is entered using the SH7751 Series standby function, and is maintained even after recovery
from standby mode other than through a power-on reset.
In the case of a power-on reset, the bus state controller’s registers are initialized, and therefore
the self-refresh state is cleared.
Rev. 3.0, 04/02, page 412 of 1064