SH7040 Datasheet, PDF (96/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.9 Instruction Formats (cont)
Instruction Formats
d format
15
xxxx xxxx dddd
0
dddd
d12 format
15
xxxx dddd
dddd
0
dddd
nd8 format
15
xxxx nnnn
dddd
0
dddd
i format
15
0
xxxx xxxx i i i i i i i i
ni format
15
0
xxxx nnnn i i i i i i i i
Source Operand Destination
Operand
Example
dddddddd:
Indirect GBR
with
displacement
R0 (Direct register) MOV.L
@(disp,GBR),R0
R0(Direct
register)
dddddddd: Indirect MOV.L
GBR with
R0,@(disp,GBR)
displacement
dddddddd: PC
relative with
displacement
R0 (Direct register) MOVA
@(disp,PC),R0
dddddddd: PC —
relative
BF
label
dddddddddddd: —
PC relative
BRA label
(label = disp +
PC)
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
iiiiiiii: Immediate
iiiiiiii: Immediate
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
R0 (Direct register) AND #imm,R0
iiiiiiii: Immediate
iiiiiiii: Immediate
—
nnnn: Direct
register
TRAPA #imm
ADD #imm,Rn
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