SH7040 Datasheet, PDF (236/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Self-Refresh: When both the RMD and RFSH bits of the RTCSR are set to 1, the CAS signal and
RAS signal are output and the DRAM enters self-refresh mode, as shown in figure 10.16. Do not
access DRAM during self-refreshes, in order to preserve DRAM data. When performing DRAM
accesses, first cancel the self-refresh, then access only after doing individual refreshes for all row
addresses within the time prescribed for the particular DRAM.
For external bus right requests during self-refreshes, to preserve DRAM data at the time of
releasing the bus rights, only CASx, RAS, and RDWR are output and the bus rights are released to
the external device with the self-refresh maintained. Consequently, do not perform DRAM
accesses from external devices at such a time.
T_Rp
CK
T_Rr1
T_Rr2
T_Rc
T_Rc
RAS
CASx
Figure 10.16 Self-Refresh Timing
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