SH7040 Datasheet, PDF (153/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 6.5 Interrupt Response Time
Item
DMAC/DTC active
judgment
Number of States
NMI, Peripheral
Module
IRQ
0 or 1
1
Compare identified inter- 2
3
rupt priority with SR mask
level
Wait for completion of
X (≥ 0)
sequence currently being
executed by CPU
Time from start of interrupt 5 + m1 + m2 + m3
exception processing until
fetch of first instruction of
exception service routine
starts
Notes
1 state required for interrupt
signals for which
DMAC/DTC activation is
possible
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Performs the PC and SR
saves and vector address
fetch.
Interrupt
response
time
Total: 7 + m1 + m2 + m3
Minimum: 10
Maximum: 12 + 2 (m1 + m2 +
m3) + m4
9 + m1 + m2 + m3
12
13 + 2 (m1 + m2 +
m3) + m4
0.35–0.42 µs at 28.7 MHz
0.67–0.70 µs at 28.7 MHz^*
Note: * When m1 = m2 = m3 = m4 = 1
m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
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