SH7040 Datasheet, PDF (172/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

8.1.2 Block Diagram
Figure 8.1 shows the DTC block diagram. DTC transfer information is located in memory.
On-chip
ROM
On-chip
RAM
On-chip
peripheral
module
CPU interrupt request
source clear control
Interrupt request
External
memory
External
device
(memory-
mapped)
Bus controller
Register
control
Activation
control
Request
priority
control
Bus interface
DTMR
DTCR
DTSAR
DTDAR
DTIAR
DTER
DTCSR
DTBR
DTC module bus
DTC
DTMR: DTC mode register
DTCR: DTC count register
DTSAR: DTC source address register
DTDAR: DTC destination address register
DTIAR: DTC initial address register
DTER: DTC enable register
DTCSR: DTC control/status register
DTBR: DTC information base register
Figure 8.1 DTC Block Diagram
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