SH7040 Datasheet, PDF (308/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 11.12 DMAC Internal Status
Item
Address Reload On
Address Reload Off
SAR
H'FFFF8408
H'FFFF840C
DAR
H'FFFFF004
H'FFFFF004
DMATCR
H'0000007C
H'0000007C
Bus rights
Released
Maintained
DMAC operation
Halted
Processing continues
Interrupts
Not issued
Not issued
Transfer request source flag clear
Executed
Not executed
Notes: 1. Interrupts are executed until the DMATCR value becomes 0, and if the IE bit of the
CHCR is set to 1, are issued regardless of whether the address reload is on or off.
2. If transfer request source flag clears are executed until the DMATCR value becomes 0,
they are executed regardless of whether the address reload is on or off.
3. Designate burst mode when using the address reload function. There are cases where
abnormal operation will result if it is executed in cycle steal mode.
4. Designate a multiple of four for the TCR value when using the address reload function.
There are cases where abnormal operation will result if anything else is designated.
To execute more than four transfers with the address reload on, make the transfer request source
issue another transfer request signal.
11.4.5 Example of DMA Transfer between External Memory and SCI1 Send Side
(Indirect Address On)
In this example, DMAC channel 3 is used, an indirect address designated external memory is the
transfer source and the SCI1 sending side is the transfer destination.
Table 11.13 indicates the transfer conditions and the setting values of each of the registers.
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