SH7040 Datasheet, PDF (600/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 15.7 A/D Conversion Times
CKS = 0
CKS = 1
Time
Symbol Min Typ Max
Min
Typ
Max
A/D conversion start
t_D
delay time
1.5 1.5 1.5
1.5
1.5
1.5
Input sampling time
t _SPL
20 20 20
40
40
40
A/D conversion time
t _CONV
42.5 42.5 42.5
82.5 82.5 82.5
Notes: 1. Unit: states
2. Table entries are for when ADST = 1. If 200 states have not elapsed since the PWR bit
has been set, no conversions are done until after those 200 states have occurred.
When PWR = 0, add 200 states to the first A/D conversion start delay time. When
continuously executing conversion, tcp for the second time and following is 20 cycle
when CKS=0 and 40 cycle when CKS=1.
The CKS bit of the ADCSR is the operation time t_CONV, but set so that this is 2 µs or greater. Table
15.8 shows the operating frequency and CKS bit settings.
Table 15.8 Operating Frequency and CKS Bit Settings
CKS
Conversion Time
(States)
28 MHz
Minimum Conversion Time (µs)
20 MHz 16 MHz 10 MHz
0
42.5
—
2.1
2.6
4.3
1
82.5
2.9
4.2
5.0
8.3
Note: The indication “—” means the setting is not available.
8 MHz
5.3
10.3
15.5 Interrupts
The high speed A/D converter generates an A/D conversion end interrupt (ADI) upon completion
of A/D conversions. The ADI interrupt request can be enabled or disabled by the ADIE bit of the
ADCSR.
The DTC or DMAC can be activated by ADI interrupts. When converted data is read by the DTC
or DMAC upon an ADI interrupt, consecutive conversions can be done without software
responsibility.
Table 15.9 lists the high speed A/D converter interrupt sources.
During scan mode, if the ADIE bit is set to 1, A/D conversion is temporarily suspended
immediately when the ADF flag is set to 1. A/D conversion is restarted when the ADF flag is
cleared to 0.
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