SH7040 Datasheet, PDF (111/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

From any state
when RES = 0
From any state when
RES = 1 and MRES = 0
Power-on reset state
RES = 0
Manual reset state
When an interrupt source
or DMA address error occurs
RES = 1
RES = 1
MRES = 1
Exception processing state
Reset states
Bus request
cleared
Bus request
generated
Bus release state
Exception
processing
source occurs
NMI interrupt
source occurs
Exception
processing
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
SBY bit
cleared
for SLEEP
instruction
Program execution state
SBY bit set
for SLEEP
instruction
Sleep mode
Standby mode
Power-down state
Figure 2.6 Transitions between Processing States
Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset
results. When the RES pin is high and MRES is low, a manual reset will occur.
Exception Processing State: The exception processing state is a transient state that occurs when
exception processing sources such as resets or interrupts alter the CPU’s processing state flow.
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