SH7040 Datasheet, PDF (903/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Appendix C Pin States
Table C.1 Pin Modes During Reset, Power-Down, and Bus Right Release Modes (144 Pin)
Pin Function
Class Pin Name
Clock CK
System RES
control _MRES
WDTOVF
BREQ
BACK
Interrupt NMI
IRQ0–IRQ7
IRQOUT (PD30)
IRQOUT (PE15)
Address A0–A21
bus
Data bus D0–D31
Bus
WAIT
control _{RD/WR, RAS}
CASH, CASL,
CASLH, CASLL
RD
CS0, CS1
CS2, CS3
WRHH, WRHL,
WRH, WRL
AH
DMAC DACK0, DACK1
(PD26, PD27)
DACK0, DACK1
(PE14, PE15)
DRAK0, DRAK1
DREQ0, DREQ1
Pin modes
Reset
Power-Down _{Bus Right}
Power-OnManual Standby Sleep Release
O
O
H^*1
OO
I
I
I
I
I
Z^*4
I
Z
I
I
O^*3
O^*3
O
OO
Z^*4
I
Z
I
I
Z^*4
O
Z
OL
I
I
I
I
I
Z^*4
I
Z
I
I
Z^*4
O
H^*1
HO
Z^*4
O
Z
HO
O^*2
O
Z
OZ
Z^*4
I/O
Z
I/O Z
Z^*4
I
Z
I
Z
Z^*4
O
O
OZ
Z^*4
O
O
OZ
H
O
Z
OZ
H
O
Z
OZ
Z^*4
O
Z
OZ
H
O
Z
OZ
Z^*4
O
Z^*4
O
Z
OZ
O^*1
OO
Z^*4
O
Z
OO
Z^*4
O
Z^*4
I
O^*1
OO
Z
I
I
Standby in Bus
Right Release
O
I
Z
O
I
L
I
Z
H^*1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
O^*1
Z
O^*1
Z
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