SH7040 Datasheet, PDF (749/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

MOV.L
Program_end
MOV.B
MOV.B
;
RTS
NOP
;
.ALIGN
PdataBuff
#OK,R7
.EQU
$
#H’00,R0
R0,@(FLMCR1,GBR)
4
.RES.B 32
; R7 <- OK (return value)
; Clear SWE
22.7.3 Erase Mode (n = 1 for Addresses H'0000–H'1FFFF, n = 2 for Addresses H'20000–
H'3FFFF)
When erasing flash memory, the erase/erase-verify flowchart shown in figure 22.14 should be
followed.
To perform data or program erasure, set the flash memory area to be erased in erase block register
n (EBRn) at least 10 µs after setting the SWE bit to 1 in flash memory control register 1
(FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program
runaway, etc. Set 5.3 µs as the WDT overflow period. After this, preparation for erase mode (erase
setup) is carried out by setting the ESUn bit in FLMCRn, and after the elapse of 200 µs or more,
the operating mode is switched to erase mode by setting the En bit in FLMCRn. The time during
which the En bit is set is the flash memory erase time. Set an erase time of 5 ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all “0”) is not necessary before starting the erase procedure.
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