SH7040 Datasheet, PDF (190/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 8.6 Execution State of DTC
Mode
Register
Information
Vector Read I Read/Write J Data Read K
Normal
1
7
1
Repeat
1
7
1
Block transfer 1
7
N
Note: N: block size (default set values of DTCRB)
Data Write L
1
1
N
Internal
Operation M
1
1
1
Table 8.7 State Counts Needed for Execution State
Access Objective
On- On-
chip chip Internal I/O
RAM ROM Register
Bus width
32 32 32
Access
state
1
1
2^*1 3^*2
Execution Vector read
S_I
state
Register information S_J
read/write
—1
—
1
1
—
Byte data read
S_K
1
1
2
3
Word data read
S_K
1
1
2
3
Long word data read S_K
1
1
4
6
Byte data write
S_L
1
1
2
3
Word data write
S_L
1
1
2
3
Long word write
S_L
1
1
4
6
Internal operation
S_M
1
Notes: *1 Two state access module : port, INT, CMT, SCI, etc.
*2 Three state access module : WDT, CACHE, UBC, etc.
External Device
8
16 32
2
2
2
4
2
2
8
4
2
2
2
2
4
2
2
8
4
2
2
2
2
4
2
2
8
4
2
The execution state count is calculated using the following formula. ∑ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is 1).
Execution state count = I · S_I + ∑ (J · S_J + K · S_K + L · S_L) + M · S_M
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