SH7040 Datasheet, PDF (372/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Procedure for Setting Buffer Mode (Figure 12.19):
1. Use the timer I/O control register (TIOR) to set the TGR as either an input capture or output
compare register.
2. Use the timer mode register (TMDR) BFA, and BFB bits to set the TGR for buffer mode.
3. Set the CST bit in the TSTR to 1 to start the count operation.
Buffer mode
Select TGR function
1
Select buffer mode
2
Start counting
3
Buffer mode
Figure 12.19 Buffer Operation Setting Procedure
Buffer Operation Examples—when TGR Is an Output Compare Register: Figure 12.20
shows an example of channel 0 set to PWM mode 1, and the TGRA and TGRC registers set for
buffer operation.
The TCNT counter is cleared by a compare-match B, and the output is a 1 upon compare-match A
and 0 output upon compare-match B. Because buffer mode is selected, a compare-match A
changes the output, and the buffer register TGRC value is simultaneously transferred to the
general register TGRA. This operation is repeated with each occurrence of a compare-match A.
See section 12.4.6, PWM Mode, for details on the PWM mode.
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