SH7040 Datasheet, PDF (211/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bits 15–8—Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00):
These bits specify idle cycles inserted between consecutive accesses when the second one is to
a different CS area after a read. Idles are used to prevent data conflict between ROM (and
other memories, which are slow to turn the read data buffer off), fast memories, and I/O
interfaces. Even when access is to the same area, idle cycles must be inserted when a read
access is followed immediately by a write access. The idle cycles to be inserted comply with
the area specification of the previous access. Refer to section 10.6, Waits between Access
Cycles, for details.
IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle
between cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and
IW01, IW00 specify the idle between cycles for CS0 space.
Bit 15 (IW31)
0
1
Bit 14 (IW30)
0
1
0
1
Description
No idle cycle after accessing CS3 space
Inserts one idle cycle after accessing CS3
space
Inserts two idle cycles after accessing CS3
space
Inserts three idle cycles after accessing CS3
space (initial value)
Bit 13 (IW21)
0
1
Bit 12 (IW20)
0
1
0
1
Description
No idle cycle after accessing CS2 space
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles (initial value)
Bit 11 (IW11)
0
1
Bit 10 (IW10)
0
1
0
1
Description
No idle cycle after accessing CS1 space
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles (initial value)
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