SH7040 Datasheet, PDF (20/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
Page
Appendix C Pin
867
States
Table C.2 Pin
Modes During Reset,
Power-Down, and
Bus Right Release
Modes (112 Pin,
120 Pin)
Description
Table amended
Pin modes
Pin Function
Class Pin Name
Reset
Power-Down _{Bus Right}
Power-On Manual Standby Sleep Release
Clock CK
O
O
H^*1
OO
System RES
control _MRES
I
I
Z^*4
I
I
I
I
Z
I
I
WDTOVF
O^*3
O^*3
O
OO
BREQ
Z^*4
I
Z
I
I
BACK
Z^*4
O
Z
OL
Interrupt NMI
I
I
I
I
I
IRQ0–IRQ7
Z^*4
I
Z
I
I
IRQOUT
Z^*4
O
Z
HO
Address A0–A21
bus
O^*2
O
Z
OZ
Data bus D0–D31
Z^*4
I/O
Z
I/O Z
Bus
WAIT
Z^*4
I
Z
I
Z
control _{RDWR, RAS}
Z^*4
O
O
OZ
CASH, CASL
Z^*4
O
O
OZ
RD
H
O
Z
OZ
CS0, CS1
H
O
Z
OZ
CS2, CS3
Z^*4
O
Z
OZ
WRH, WRL
H
O
Z
OZ
AH
Z^*4
O
Z
OZ
DMAC DACK0–DACK1 Z^*4
O
Z
OO
DRAK0–DRAK1 Z^*4
O
Z
OO
DREQ0–DREQ1 Z^*4
I
Z
I
I
MTU
TIOC0A–TIOC0D, Z^*4
TIOC1A–TIOC1D,
TIOC2A–TIOC2D,
TIOC3A, TIOC3C
I/O
K^*1
I/O I/O
TIOC3B,TIOC3D, Z^*4
TIOC4A–TIOC4D
I/O
Z
I/O I/O
TCLKA–TCLKD Z^*4
I
Z
I
I
Standby in Bus
Right Release
O
I
Z
O
I
L
I
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
K^*1
Z
Z