SH7040 Datasheet, PDF (513/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the
asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the
clock synchronous mode because no stop bits are added.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit
of the next incoming character.
Bit 3: STOP
0
1
Description
One stop bit (initial value). In transmitting, a single bit of 1 is added at
the end of each transmitted character.
Two stop bits. In transmitting, two bits of 1 are added at the end of each
transmitted character.
• Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor
format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored.
The MP bit setting is used only in the asynchronous mode; it is ignored in the clock
synchronous mode. For the multiprocessor communication function, see section 14.3.3,
Multiprocessor Communication.
Bit 2: MP
0
1
Description
Multiprocessor function disabled (initial value)
Multiprocessor format selected
• Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available; φ, φ/4, φ/16, or
φ/64. For further information on the clock source, bit rate register settings, and baud rate, see
section 14.2.8, Bit Rate Register (BRR).
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
φ (initial value)
φ/4
φ/16
φ/64
475