SH7040 Datasheet, PDF (291/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with
dual address and level detection is virtually the same as that of cycle steal mode.
For example, DMAC transfer begins (figure 11.19), at the earliest, three cycles after the timing of
the first sampling. The second sampling also begins from the start of the transfer one bus cycle
before the start of the first DMAC transfer. In burst mode, as long as transfer requests are issued,
DMAC transfer continues. Therefore, the “transfer one bus cycle before the start of the DMAC
transfer” may be a DMAC transfer.
In burst mode, the DACK output period is the same as that of cycle steal mode. Figure 11.20
shows the normal operation of this burst mode.
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