SH7040 Datasheet, PDF (40/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

 Instruction length: 16-bit fixed length for improved code efficiency
 Load-store architecture (basic operations are executed between registers)
 Delayed branch instructions reduce pipeline disruption during branch
 Instruction set based on C language
• Instruction execution time: one instruction/cycle (35 ns/instruction at 28.7-MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) and
multiplication/accumulation operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two
to four cycles
• Five-stage pipeline
Cache Memory:
• 1-kbyte instruction cache
• Caching of instruction codes and PC relative read data
• 4-byte line length (1 longword: 2 instruction lengths)
• 256 entry cache tags
• Direct map method
• On-chip ROM/RAM, and on-chip I/O areas not objects of cache
• Used in common with on-chip RAM; 2 kbytes of on-chip RAM used as address array/data
array when cache is enabled
Interrupt Controller (INTC):
• Nine external interrupt pins (NMI, IRQ0–IRQ7)
• Forty-three internal interrupt sources (forty-four for A mask)
• Sixteen programmable priority levels
User Break Controller (UBC):
• Generates an interrupt when the CPU or DMAC generates a bus cycle with specified
conditions
• Simplifies configuration of an on-chip debugger
Bus State Controller (BSC):
• Supports external extended memory access
 16-bit (QFP-112, TQFP-120), or 32-bit (QFP-144) external data bus
• Memory address space divided into five areas (four areas of SRAM space, one area of DRAM
space) with the following settable features:
 Bus size (8, 16, or 32 bits)
 Number of wait cycles
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