SH7040 Datasheet, PDF (738/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

700
Start
Set pin to the boot program mode
then reset start
The host continuously sends data
(H'00) using a fixed bit rate
This LSI measures the low period
of data H'00 sent by the host
This LSI calculates the bit rate and
sets value to the bit rate register
After adjustment of the bit rate, this
LSI sends 1 byte of data H'00 to the
host as a sign of completion of adjustment
The host checks whether the sign
(H'00) indicating completion of bit
rate adjustment is received, then
transmits 1 byte of data H'55
After receiving H'55, this LSI sends
1 byte of H'AA
The host sends the byte number
(N) of the user program in sequence
of upper byte then lower byte
This LSI sends the received byte
number to the host as verify data
(echo back)
n=1
The host transmits the user program
in sequence using byte units
This LSI sends the received
program to the host as verify data
(echo back)
The received user program is
transferred to the on-chip RAM
No
n=N?
Yes
Transmission complete
Data of the flash memory is
checked. All data are erased if
data already exists
After confirming that all data of the
flash memory have been erased,
this LSI sends 1 byte of H'AA to the host
The write control program transferred
to the on-chip RAM is executed
n+1→n
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 22.9 Boot Mode Execution Procedure