SH7040 Datasheet, PDF (507/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section 14 Serial Communication Interface (SCI)
14.1 Overview
The SH7040 Series has a serial communication interface (SCI) with two independent channels,
both of which possess the same functions.
The SCI supports both asynchronous and clock synchronous serial communication. It also has a
multiprocessor communication function for serial communication among two or more processors.
14.1.1 Features
• Select asynchronous or clock synchronous as the serial communications mode.
 Asynchronous mode: Serial data communications are synched by start-stop in character
units. The SCI can communicate with a universal asynchronous receiver/transmitter
(UART), an asynchronous communication interface adapter (ACIA), or any other chip that
employs a standard asynchronous serial communication. It can also communicate with two
or more other processors using the multiprocessor communication function. There are
twelve selectable serial data communication formats.
Data length: seven or eight bits
Stop bit length: one or two bits
Parity: even, odd, or none
Multiprocessor bit: one or none
Receive error detection: parity, overrun, and framing errors
Break detection: by reading the RxD level directly when a framing error occurs
 Clocked synchronous mode: Serial data communication is synchronized with a clock
signal. The SCI can communicate with other chips having a clock synchronous
communication function. There is one serial data communication format.
Data length: eight bits
Receive error detection: overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use double buffering, so
continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates.
• Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin
(external).
• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-
error interrupts are requested independently. The transmit-data-empty and receive-data-full
interrupts can start the direct memory access controller (DMAC)/data transfer controller (DTC)
to transfer data.
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