SH7040 Datasheet, PDF(398/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (398/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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â¢ Initialization

In complementary PWM mode, there are six registers that must be initialized.

Before setting complementary PWM mode with bits MD3âMD0 in the timer mode register

(TMDR), the following initial register values must be set.

TGR3C operates as the buffer register for TGR3A, and should be set with 1/2 the PWM carrier

cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for

the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set

dead time Td in the timer dead time data register (TDDR).

Set the respective initial PWM duty values in buffer registers TGR3D, TGR4C, and TGR4D.

The values set in the five buffer registers excluding TDDR are transferred simultaneously to

the corresponding compare registers when complementary PWM mode is set.

Set TCNT4 to H'0000 before setting complementary PWM mode.

Table 12.17 Registers and Counters Requiring Initialization

Register/Counter

Set Value

TGR3C

1/2 PWM carrier cycle + dead time Td

TDDR

Dead time Td

TCBR

1/2 PWM carrier cycle

TGR3D, TGR4C, TGR4D

Initial PWM duty value for each phase

TCNT4

H'0000

Note: The TGR3C set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead

time Td set in TDDR.

â¢ PWM output level setting

In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP

in the timer output control register (TOCR).

The output level can be set for each of the three positive phases and three negative phases of 6-

phase output.

Complementary PWM mode should be cleared before setting or changing output levels.

â¢ Dead time setting

In complementary PWM mode, PWM pulses are output with a non-overlapping relationship

between the positive and negative phases. This non-overlap time is called the dead time.

The non-overlap time is set in the timer dead time data register (TDDR). The value set in

TDDR is used as the TCNT3 counter start value, and creates non-overlap between TCNT3 and

TCNT4. Complementary PWM mode should be cleared before changing the contents of

TDDR.

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