SH7040 Datasheet, PDF (217/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Bit:
Initial value:
R/W:
15
TPC
0
R/W
14
RCD
0
R/W
13
12
TRAS1 TRAS0
0
0
R/W R/W
11
DWW1
0
R/W
10
DWW0
0
R/W
9
DWR1
0
R/W
8
DWR0
0
R/W
Bit: 7
6
5
4
3
2
1
0
DIW
—
BE RASD SZ1
SZ0 AMX1 AMX0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W R/W R/W R/W R/W R/W
• Bit 15—RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after
RAS is negated before next assert.
Bit 15 (TPC)
0
1
Description
1.5 cycles (initial value)
2.5 cycles
• Bit 14—RAS-CAS Delay Cycle Count (RCD): Specifies the number of row address output
cycles.
Bit 14 (RCD)
0
1
Description
1 cycle (initial value)
2 cycles
• Bits 13–12—CAS-Before-RAS Refresh RAS Assert Cycle Count (TRAS1–TRAS0): Specify
the number of RAS assert cycles for CAS before RAS refreshes.
Bit 13 (TRAS1)
0
1
Bit 12 (TRAS0)
0
1
0
1
Description
2.5 cycles (initial value)
3.5 cycles
4.5 cycles
5.5 cycles
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