SH7040 Datasheet, PDF (627/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

17.1.3 Register Configuration
Table 17.1 summarizes the CMT register configuration.
Table 17.1 Register Configuration
Channel Name
Abbreviation R/W
Initial
Value Address
Access Size
(Bits)
Shared Compare match timer CMSTR
start register
R/W H'0000 H'FFFF83D0 8, 16, 32
0
Compare match timer CMCSR0
R/(W)^* H'0000 H'FFFF83D2 8, 16, 32
control/status register 0
Compare match timer CMCNT0
counter 0
R/W H'0000 H'FFFF83D4 8, 16, 32
Compare match timer CMCOR0
constant register 0
R/W H'FFFF H'FFFF83D6 8, 16, 32
1
Compare match timer CMCSR1
R/(W)^* H'0000 H'FFFF83D8 8, 16, 32
control/status register 1
Compare match timer CMCNT1
counter 1
R/W H'0000 H'FFFF83DA 8, 16, 32
Compare match timer CMCOR1
constant register 1
R/W H'FFFF H'FFFF83DC 8, 16, 32
Note: * The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to clear
the flags.
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