SH7040 Datasheet, PDF (419/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

φ
External
clock
TCNT
input clock
Falling edge
Rising edge
Falling edge
TCNT
N–1
N
N+1
Figure 12.61 TCNT Count Timing during External Clock Operation (Phase Counting
Mode)
Output Compare Output Timing: The compare-match signal is generated at the final state of
TCNT and TGR matching. When a compare-match signal is issued, the output value set in TIOR
or TOCR is output to the output compare output pin (TIOC pin). After TCNT and TGR matching,
a compare-match signal is not issued until immediately before the TCNT input clock.
Output compare output timing (normal mode and PWM mode) is shown in figure 12.62. See
figure 12.63 for output compare output timing in complementary PWM mode and reset sync
PWM mode.
φ
TCNT
input clock
TCNT
N
N+1
TGR
N
Compare-
match signal
TIOC pin
Figure 12.62 Output Compare Output Timing (Normal Mode/PWM Mode)
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