SH7040 Datasheet, PDF (178/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Bit: 15
14
8
DTCRAH
Initial value: *
*
*
*
*
*
*
*
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
0
DTCRAL
Initial value: *
*
*
*
*
*
*
*
R/W: —
—
—
—
—
—
—
—
Note: * Initial value is undefined.
8.2.6 DTC Transfer Count Register B (DTCRB)
The DTCRB is a 16-bit register that designates the block length in block transfer mode. The
contents of this register is located in memory. The block length is 1 when the set value is H'0001,
65535 when it is H'FFFF, and 65536 when it is H'0000.
Bit: 15
14
13
12
11
10
9
8
Initial value: *
*
*
*
*
*
*
*
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Initial value: *
*
*
*
*
*
*
*
R/W: —
—
—
—
—
—
—
—
Note: * Initial value is undefined.
8.2.7 DTC Enable Registers (DTER)
The DTER (DTEA–DTEE) are five 8-bit readable/writable registers with bits allocated to each
interrupt source that activates the DTC. They set disable/enable for DTC activation for each
interrupt source. When a bit is 1, DTC activation by the corresponding interrupt source is enabled.
Interrupt sources for each of the DTEA–DTEE registers are indicated in table 8.2.
The DTER are initialized to H'00 by a power-on reset or in standby mode. Manual reset does not
initialize DTER.
140