SH7040 Datasheet, PDF (228/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

10.4.2 Basic Timing
The SH7040 Series supports 2 CAS format DRAM access. The DRAM access basic timing is a
minimum of 3 cycles for normal mode. Figure 10.7 shows the basic DRAM access timing. DRAM
space access is controlled by RAS, CASx, and RDWR signals. The following signals are
associated with transfer of these actual byte locations: CASHH (bits 31–24), CASHL (bits 23–16),
CASH (bits 15–8), and CASL (bits 7–0). However, the signals for ordinary space, WRx and RD,
are also output during the DMAC single transfer column address cycle period. T_p is the precharge
cycle, T_r is the RAS assert cycle, T_c is the CAS assert cycle and T_c2 is the read data fetch cycle.
T_p
T_r
T_c1
T_c2
CK
Address
Row
Column
Write
Data
RAS
CASx
RDWR
Read
Data
RAS
CASx
RDWR
Figure 10.7 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, No Waits)
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