SH7040 Datasheet, PDF (322/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Channels 0, 3, 4:
Bit 7: Bit 6: Bit 5:
CCLR2 CCLR1 CCLR0 Description
0
0
0
TCNT clear disabled (initial value)
1
TCNT is cleared by TGRA compare-match or input capture
1
0
TCNT is cleared by TGRB compare-match or input capture
1
Synchronizing clear: TCNT is cleared in synchronization with clear of
other channel counters operating in sync.^*1
1
0
0
TCNT clear disabled
1
TCNT is cleared by TGRC compare-match or input capture^*2
1
0
TCNT is cleared by TGRD compare-match or input capture^*2
1
Synchronizing clear: TCNT is cleared in synchronization with clear of
other channel counters operating in sync^*1
Notes: *1 Setting the SYNC bit of the TSYR to 1 sets the synchronization.
*2 When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because
the buffer registers have priority and compare-match/input captures do not occur.
Channels 1, 2:
Bit 7:
Bit 6:
Bit 5:
Reserved^*1 CCLR1 CCLR0 Description
0
0
0
TCNT clear disabled (initial value)
1
TCNT is cleared by TGRA compare-match or input capture
1
0
TCNT is cleared by TGRB compare-match or input capture
1
Synchronizing clear: TCNT is cleared in synchronization with
clear of other channel counters operating in sync^*2
Notes: *1 The bit 7 of channels 1 and 2 is reserved. It always reads 0, and cannot be modified.
*2 Setting the SYNC bit of the TSYR to 1 sets the synchronization.
• Bits 4–3—Clock Edge 1, 0 (CKEG1 and CKEG0): CKEG1 and CKEG0 select the input clock
edges. When counting is done on both edges of the internal clock the input clock frequency
becomes 1/2 (Example: both edges of φ/4 = rising edge of φ/2). When phase count mode is
used with channels 1, 2, these settings are ignored, as the phase count mode settings have
priority.
284