SH7040 Datasheet, PDF (181/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

8.2.9 DTC Information Base Register (DTBR)
The DTBR is a 16-bit readable/writable register that specifies the upper 16 bits of the memory
address containing DTC transfer information. Always access the DTBR in word or longword
units. If it is accessed in byte units the register contents will become undefined at the time of a
write, and undefined values will be read out upon reads.
The DTBR is not initialized either by resets or in standby mode.
Bit: 15
14
13
12
11
10
9
8
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: *
*
*
*
*
*
*
*
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Initial value is undefined.
8.3 Operation
The DTC stores transfer information in memory. When there are DTC transfer requests, it reads
that transfer information and performs data transfers based on it. It rewrites the transfer
information to memory after data transfers. Storing transfer information in memory makes it
possible to perform data transfers for an arbitrary number of channels. Further, setting the CHNE
bit to 1 makes it possible to perform multiple transfers continuously through one DTC transfer
request.
There are three DTC transfer modes: normal mode, repeat mode, and block transfer mode. After a
DTC transfer, the transfer source address and transfer destination address are incremented,
decremented, or kept the same, according to the respective setting.
8.3.1 Overview of Operation
Figure 8.2 shows a flowchart of DTC operation.
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