SH7040 Datasheet, PDF (612/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Channel
Selection
CH1
0
1
CH0
0
1
0
1
Single mode
A/D0
AN0
(Initial value)
AN1
AN2
AN3
Description
Scan mode
A/D1
A/D0
AN4
AN0
(Initial value)
AN5
AN0, AN1
AN6
AN0, AN1
AN7
AN0–AN3
A/D1
AN4
AN4, AN5
AN4–AN6
AN4–AN7
16.2.3 A/D Control Register (ADCR0, ADCR1)
A/D control registers (ADCR0, 1) are registers that can read/write in 8 bits and enables or disables
A/D conversion start of the external trigger input. There are the ADCR0 (A/D0) and ADCR1
(A/D1).
ADCR is initialized to H'7F during power-on reset and standby mode. Manual reset does not
initialize ADCR.
Bit :
7
6
5
4
3
2
1
0
Initial value : TRGE
—
—
—
—
—
—
—
0
1
1
1
1
1
1
1
R/W : R/W
R
R
R
R
R
R
R
• Bit 7—Trigger Enable (TRGE): Enables or disables A/D conversion start of input from
external or MTU trigger.
Bit 7:
TRGE
0
1
Description
Disables A/D conversion start of external or MTU trigger
(Initial value)
Starts A/D conversion on last transition edge of A/D conversion trigger input pin
(ADTRG) or MTU trigger.
A/D0 and A/D1 are common for external trigger pin and MTU trigger.
A/D0 and A/D1 settings are of logical sum.
• Bits 6–0—Reserved bits: These bits always read as 1. The write value should always be 1.
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