SH7040 Datasheet, PDF (424/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

φ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 12.70 TGI Interrupt Timing (Input Capture)
Setting Timing for Overflow Flag (TCFV)/Underflow Flag (TCFU): Figure 12.71 shows
timing for the TCFV flag of the timer status register (TSR) due to overflow, as well as TCIV
interrupt request signal timing. Figure 12.72 shows timing for the TCFU flag of the timer status
register (TSR) due to underflow, as well as TCIU interrupt request signal timing. Figure 12.73
shows timing for the TCFV flag of TSR4 due to underflow in complementary PWM mode, as well
as TCIV interrupt request signal timing.
φ
TCNT
input clock
TCNT
(underflow)
Overflow
signal
TCFV flag
H'FFFF
H'0000
TCIV interrupt
386
Figure 12.71 TCIV Interrupt Setting Timing