SH7040 Datasheet, PDF (403/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT3, 4 value
TCNT3
TCNT4
Positive phase
output
Negative phase
output
TDDR
TGR4A
Initial output
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT3, 4 count start
(TSTR setting)
Figure 12.44 Example of Initial Output in Complementary PWM Mode (2)
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