SH7040 Datasheet, PDF (768/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

A16-0
CE
Command write
t_ces
t_ceh
t_nxtc
Memory read mode
Address stable
OE
WE
I/O7-0
t_wep
t_f
t_r
t_ds
t_dh
Note: Data is latched on the rising edge of WE.
Figure 22.21 Timing Waveforms for Memory Read after Memory Write
Table 22.14 AC Characteristics in Transition from Memory Read Mode to Another Mode
(Conditions: V_CC = 5.0 V ±10%, V_SS = 0 V, T_a = 25°C ±5°C)
Item
Command write cycle
CE hold time
CE setup time
Data hold time
Data setup time
Write pulse width
WE rise time
WE fall time
Symbol
t _nxtc
t _ceh
t _ces
t _dh
t _ds
t _wep
t_r
t_f
Min
20
0
0
50
50
70
Max
Unit
Notes
µs
ns
ns
ns
ns
ns
30
ns
30
ns
730