SH7040 Datasheet, PDF(133/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (133/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Table 5.9 Types of Exceptions Triggered by Instructions

Type

Source Instruction

Trap instructions TRAPA

Illegal slot

instructions

Undefined code placed

immediately after a delayed

branch instruction (delay slot)

and instructions that rewrite the

PC

General illegal

instructions

Undefined code anywhere

besides in a delay slot

Comment

â

Delayed branch instructions: JMP, JSR,

BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

Instructions that rewrite the PC: JMP, JSR,

BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF

â

5.5.1 Trap Instructions

When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

3. The exception service routine start address is fetched from the exception processing vector

table that corresponds to the vector number specified in the TRAPA instruction. That address

is jumped to and the program starts executing. The jump that occurs is not a delayed branch.

5.5.2 Illegal Slot Instructions

An instruction placed immediately after a delayed branch instruction is said to be placed in a delay

slot. When the instruction placed in the delay slot is undefined code, illegal slot exception

processing starts up when that undefined code is decoded. Illegal slot exception processing also

starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The

processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as

follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the

delayed branch instruction immediately before the undefined code or the instruction that

rewrites the PC.

3. The exception service routine start address is fetched from the exception processing vector

table that corresponds to the exception that occurred. That address is jumped to and the

program starts executing. The jump that occurs is not a delayed branch.

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