SH7040 Datasheet, PDF (804/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

CK
A21–A0
RAS
CASxx
(During read)
RDWR
(During read)
D31–D0
(During read)
CASxx
(During write)
RDWR
(During write)
D31–D0
(During write)
DACKn
RD
(During read)
WRxx
(During write)
CK
RAS
CASxx
Tp
Tr
Tc1
Tc2
Tc1
Tc2
t_AD
t_AD
Row address
t_ASR
t_RASD1
t_RAH
t_RP
Column address
t_CASD1
t_CASD2
Column address
t_RASD2
t_CASD1
t_CP
tCASD2
t_RAC
t_CAC
t_AA
t_RDS
t_AA
t_RDH
t_CAC
t_RDS
t_RDH
t_CASD1
t_RWD1
t_CASD2
t_RWD2
t_CASD1
t_CP
t_RWD1
t_CASD2
t_RWD2
t_DS
t_WDD
t_DACKD1
t_DH
t_WDH
t_DS
t_WDD
t_DACKD1
t_DH
t_WDH
t_DACKD1
t_RSD1
t_WSD1
t_RSD2
t_RSD1
t_WSD2
t_WSD1
t_RSD2
t_WSD2
Note: t_RDH is specified from fastest negate timing of A21–A0, RAS, and CAS.
Figure 25.16 DRAM Cycle (High-Speed Page Mode)
TRp
TRr1
TRr2
TRc
TRc
t_CASD1
t_CSR
t_RASD1
t_RASD2
t_CASD2
RDWR
Figure 25.17 CAS Before RAS Refresh (TRAS1 = 0, TRAS0 = 0)
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