SH7040 Datasheet, PDF (218/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bits 11–10—DRAM Write Cycle Wait Count (DWW1–DWW0): Specifies the number of
DRAM write cycle column address output cycles.
Bit 11 (DWW1)
0
1
Bit 10 (DWW0)
0
1
0
1
Description
2-cycle (no wait) external wait disabled (initial value)
3-cycle (1 wait) external wait disabled
4-cycle (2 wait) external wait enabled
5-cycle (3 wait) external wait enabled
• Bits 9–8—DRAM Read Cycle Wait Count (DWR1–DWR0): Specifies the number of DRAM
read cycle column address output cycles.
Bit 9 (DWR1)
0
1
Bit 8 (DWR0)
0
1
0
1
Description
2-cycle (no wait) external wait disabled (initial value)
3-cycle (1 wait) external wait disabled
4-cycle (2 wait) external wait enabled
5-cycle (3 wait) external wait enabled
• Bit 7—DRAM Idle Cycle Count (DIW): Specifies whether to insert idle cycles, either when
accessing a different external space (CS space) or when doing a DRAM write, after DRAM
reads.
Bit 7 (DIW)
Description
0
No idle cycles (initial value)
1
1 idle cycle
• Bit 6—Reserved: This bit always reads as 0. The write value should always be 0.
• Bit 5—Burst Enable (BE): Specifies the DRAM operation mode.
Bit 5 (BE)
0
1
Description
Burst disabled (initial value)
DRAM high-speed page mode enabled.
• Bit 4—RAS Down Mode (RASD): Specifies the DRAM operation mode.
Bit 4 (RASD)
0
1
Description
Access DRAM by RAS up mode (initial value)
Access DRAM by RAS down mode
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