SH7040 Datasheet, PDF(252/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (252/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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ï£§ Channel 3: Dual address mode only. Direct address transfer mode and indirect address

transfer mode selectable.

â¢ Reload function: Enables automatic reloading of the value set in the first source address

register every fourth DMA transfer. This function can be executed on channel 2 only.

â¢ Transfer requests: There are three DMAC transfer activation requests, as indicated below.

ï£§ External request: From two DREQ pins. DREQ can be detected either by falling edge or by

low level. External requests can only be received on channels 0 or 1.

ï£§ Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as

SCI or A/D. These can be received by all channels.

ï£§ Auto-request: The transfer request is generated automatically within the DMAC.

â¢ Selectable bus modes: Cycle-steal mode or burst mode

â¢ Two types of DMAC channel priority ranking:

ï£§ Fixed priority mode: Always fixed

ï£§ Round robin mode: Sets the lowest priority level for the channel that received the execution

request last

â¢ CPU can be interrupted when the specified number of data transfers are complete.

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